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L6239
12V DISK DRIVE SPINDLE DRIVER
PRODUCT PREVIEW
General 12V OPERATION REGISTER BASED ARCHITECTURE SLEEP AND IDLE MODES FOR LOW POWER CONSUMPTION SERIAL INTERFACE Spindle Driver BEMF PROCESSING FOR SENSOR-LESS MOTOR COMMUTATION INTERNAL POWER DEVICES PROGRAMMABLE SLEW-RATE FOR REDUCED E.M.I. 20 FOR ANY HALF BRIDGE WORST CASE (1 PER DEVICE) B.E.M.F. DETECTION READABLE FROM REGISTER OR PIN NO SNUBBERS REQUIRED FOR LOOP COMPENSATION OR E.M.I. CONTROL Other Functions POWER UP SEQUENCING POWER DOWN SEQUENCING PWM OPERATION LOW VOLTAGE SENSE DYNAMIC BRAKE THERMAL WARNING THERMAL SHUTDOWN NEGATIVE VOLTAGE REGULATOR SUPPORT DESCRIPTION The L6239 is a single chip sensorless (DC) spindle motor controller including power stages suitable for use in disk drives. The device has a serial interface for a microprocessor running up to 10 mega bits per second. There are registers on chip to allow the setting of the desired operating modes No external components are required in the sensor-less operation as the control functions are integrated on chip (e.g.
March 1995
MULTIPOWER BCD TECHNOLOGY
PLCC44
ORDERING NUMBER: L6239
B.E.M.F. processing & digital masking). When a power On Reset (P.O.R.) is accepted, the internal registers are reset, the spindle power circuitry is tri-stated, and dynamic braking of the spindle is applied. This device is built in BCD II technology allowing dense digital/analog circuitry to be combined with high power DMOS output stage. PIN CONNECTION
Rsense1 Rsense3 Rsense2 Out C Out C Out A Out A Out B Out B
GND
6 GND Vpower Vpower Cpump1 Vpump Cpump2 Vanalog bemf_det Vreg_Base Vreg_Vsense GND 7 8 9 10 11 12 13 14 15 16 17
5
4
3
2
1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GND AGND N.C. Ctr Tap CSA Input PWM/Slew gm Comp Gate Drive PWM Timer N.C. GND
18 19 20 21 22 23 24 25 26 27 28 SYS CLOCK SDIO POR Seq. Increment Vreg_Isense Vdgtl R/W Sclk SLoad Brake N.C.
D95IN222
GND
1/13
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
L6239
FEATURES General POWER UP MICROPROCESSOR RESET SEQUENCING - POWER UP RESET AND DELAY - INTERNAL REGISTER INITIALIZATION OVER TEMPERATURE PROTECTION MASKING ON CHIP COMMUTATION EXTERNALLY CONTROLLED NEGATIVE VOLTAGE SUPPORT CIRCUITRY Interface SERIAL SYNCHRONOUS - SCLK, SLOAD, SDIO, R/W - UP TO 10 MEGABIT DATA RATE Spindle Driver INTERNAL POWER DEVICES THREE PHASE BRIDGE PLUS BIPOLAR DRIVER BLOCK DIAGRAM
Vdgtl 21 13 VRef & Bias PWM/Linear spin_range POR R/W SDIO SLoad Sclk 24 25 22 27 26 xout, yout, zout 19 6-STATE GRAY CODE COUNTER 3 bemf_A,B,C bemf_det SYS CLOCK 14 20 SYSTEM CLOCK 8 Ds7 ..Ds0 Spin DAC xin, yin, zin single/multi_ SERIAL INTERFACE CONTROL REGISTER THERMAL SHUTDOWM PWM/Slew 34 PWM Timer 31 LINEAR SLEW RATE CONTROL & PWM MONOSTABLE CHARGE PUMP 10 12 11 POWER STAGE 8 9 Vpower Cpump1 Cpump2 Vpump
- MICROPROCESSOR SPIN-UP & SPEED CONTROL - MICROPROCESSOR INITIATED STARTUP - SPEED COMPENSATION BY EXTERNAL RC NETWORK - NO SNUBBERS REQUIRED FOR CURRENT LOOP COMPENSATION OR EMI CONTROL - MICROPROCESSOR ACCELERATION CONTROL VIA DAC (FOR SMOOTH TRANSITION TO AT SPEED CONTROL) - GRAY CODE COUNTER FOR COMMUTATION CONTROL (INCREMENTED BY SPIN_CLOCK PIN). - BEMF DETECTION READABLE FROM REGISTERS (A,B OR C PHASES) OR PIN (BEMF_DET). AUTOMATIC CLAMPING OF OUTPUT TO PREVENT SUBSTRATE CURRENT PROGRAMMABLE SLEW RATE CONTROL (LINEAR MODE ONLY) 8 BIT RESOLUTION SPINDLE DAC FOR MICROPROCESSOR ACCELERATION CONTROL DYNAMIC BRAKING BY COMMAND
Vanalog
23 4 5 1 + 2 41 42 36 3 43 44
Brake Out A
Sequence Increment
Out B
enable_clk
ZERO CROSSING DETECTOR
BEMF + SENSE
Out C Ctr Tap Rsense1 Rsense2 Rsense3
+ -
+ 6,7,17,29,39,40 DRV CNTL 38 35 GND AGND CSA Input
Vreg_Base Vreg_Isense Vreg_Vsense
15 18 16
NEGATIVE VOLTAGE REGULATOR
To PWM Monostable + PWM COMP. 33 gm Comp
AV=4V/V CSA
32 Gate Drive
D95IN218A
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L6239
ABSOLUTE MAXIMUM RATINGS
Symbol VS VS VImax VI min Ipeak/Idc Ptot Tstg , Tj Parameter Maximum Supply Voltage (Vanalog, power max) Maximum Supply Voltage (Vdigital max) Maximum Input Voltage Minimum Input Voltage Peak Sink/Source Output Current/DC Sink Source Output Current Maximum Total Power Dissipation Maximum Storage and Junction Temperature Range Value 15 7 Vdigital 0.3 GND - 0.5 2.2 3 -40 to 150 Unit V V V V A W C
THERMAL DATA
Symbol Rth j-amb Parameter Thermal Resistance Junction-ambient (standard PCB mounted) Value 27 Unit C/W
Note: This standard board construction includes: A 4 layer board, for 1cm2 hest copper area best sinks located at the chips vertices each with 4 rows of 4 columns of plated vias (od = 0.104cm, diameter = 0.0584cm) through to the ground plane.
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L6239
PIN DESCRIPTION Pin Types: I = Input, O = Output, P = Power, A = Analog (passive)
N. Name Function Pin Type
POWER
6, 7, 17, 29, 40 38 8, 9,37 13 21 Ground Analog Ground VPower VAnalog Vdgtl Power Ground Analog Signal Return Driver Power Supply (12V) Analog Supply (12V) Logic Supply (5V) AI AI AI AI AI
SERIAL INTERFACE, DIGITAL & TEST PINS
22 25 27 26 19 23 24 14 20 28 30 SDIO R/W SLoad SCLK Sequence Increment Brake POR BEMF det SYS CLK TP out1 TP out2 Serial Port Data I/O Serial Port Read/Write Input Serial Port Chip Select. Port is selected when low Serial Port Clock Increments the spindle commutation on low to high transition Applies braking (all low side drivers energized) after the timedefined by Brake_time. Active low Resets the controller on receipt of POR low Post masching BEMF zero crossing signal Sistem clock Test pin 1 Test pin 2 DI/O DI DI DI DI DI DI DO DI TO TO
ANALOG PINS
4, 5 1, 2 41, 42 36 3, 43, 44 35 33 32 10 12 11 34 31 15 18 16 Coil A Coil B Coil C Center Tap Rsense CSA Input GM Comp Gate Drive (NOTE 1) Cpump 1 Cpump 2 Vpump PWM/ Slew PWM Timer Vreg Base Vreg Isense Vreg Vsense Motor Coil Driver for phase A. This pin is also used for sensing the BEMF As above for phase B As above for phase C Center tap motor connection Sense Resistor Pins Current Sense Amplifier Input for sensing of voltage across the external sense resistor. A series RC network to ground that defines the compensation for the Transconductance Loop For external PMOS applications Positive terminal of the pump capacitor Negative terminal of the pump capacitor Charge pump output An RC network to GND defines the slew ate from this pin Masking for PWM (max) Negative voltage regulator - Base Negative voltage regulator - Current input Negative voltage regulator - Regulator AI/O AI/O AI/O AI/O AI/O AI/O AO AI/O A/O A/O A/O AO AO A/O AI AI
NOTE 1: for internal mode, this pin must be grounded. For external mode, connect this pin to the external PMOS.
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L6239
ELECTRICAL CHARACTERISTICS (Tamb = 0 to 70C; VA = Vpower = 12V; Vdigital = 5V, unless otherwise specified. Parameters market with an * are guaranteed by design, but not 100% tested in production)
Symbol Parameter Test Condition Min. Typ. Max. Unit
GENERAL
Vanalog, Power Vdigital Iready12 Isleep12 Iready5 Isleep5 Supply Voltage Range Supply Voltage Range Quiescent Current Quiescent Current Quiescent Current Quiescent Current Spindle Enabled Spindle Disabled Spindle Enabled Spindle Disabled 10 4.5 12 5 13.6 5.5 15 1000 5 1000 V V mA A mA A C C
THERMAL SHUTDOWN
*ThWarn *ThSh Dwn Thermal Warning Thermal Shutdown 130 155 150 175 170 195
SPINDLE DRIVER SECTION
Io dv/dt on R DS(on) Total RDS(on) Device Io (LEAK) VF dVo/dt Maximum Output Current Voltage Sew Rate Total Output On Resistance (Sink + Source) Sink Output On Resistance Output Leakage Current Body Diode Forward Drop Output Slew Rate Im = 2.0A Im = 100mA R slew = 100K 0.30 Turn on Turn off Tj = 25C, Tj = 125C, Iload = 2.0A Tj = 25C, Tj = 125C, Iload = 2.0A 2.2 0.2 0.1* 1.0 0.5 2.0 1.0* 2.0 1.0 1 1.5 0.9 0.35 A V/s V/s mA V V V/s
* Yet to be confirmed
DAC ACCELERATION CONTROL / SENSE AMPLIFIER
RES NL INL FS CT FSCT Gain DAC out OFFSET Resolution Differential Non-linearity Integral Non- linearity Full Scale Accuracy Conversion Time Full Scale Temp Coefficient Curr. Sense Gain Ratio 4:1 or 20:1 DAC Output Input Offset of Sense Amp 0 to 125C 1% resistence tolerance (0.5) 0 0 7 Full scale 0-1 bit excluded 8 0.5 1.5 5 10 250 TBD 2 15 bits LSB LSB % s ppm/C % V mV
LOGIC SECTION (All digital inputs are CMOS compatible)
Vih Vil Voh Vol Iin Iwsi Fsys High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Minimum Sequence Increment High Time System Clock Frequency Iout = 1.0mA Iout = 1.0mA Tj = 125C, 1 -1 Note 1 10.0 MHz 4.5 0.4 1 3.5 1.5 V V V V mA
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L6239
ELECTRICAL CHARACTERISTICS (continued)
Symbol C in C in PORIN Parameter Logic Input Capacitance (except Serial Port Clock) Serial Port Clock Input Capacitance (Logic Level Low) POR Pulse Width Test Condition All inputs except SCLK SCLK 1 Min. Typ. Max. 5 10 Unit pF pF s
4 Note1: The minimum time that the Sequence Increment pin must be held high during eternal sequence incrementing is equal to SysCk
BEMF AMPLIFIER
IAmpin VBEMF VOFF_HYST Input Bias Current Minimum Bemf (Pk-Pk) Voltage Offset Hysteresis 60 11 18 25 10.0 A mV mV
BRAKE
Tbrake Ibrlk Ibrin Time from POR signal receipt to expected receipt of Brake signal Brake Leakage Current Brake Low Input Current 100 0.01 500 10 ms A A A s V V A s V mV
NEGATIVE VOLTAGE REGULATOR - CURRENT SENSE COMPARATOR
Ibias Tresp HighTh LowTh Input Bias Current Response Time High hysteresis threshold Low Hysteresis Threshold 0.3V input 20mV overdrive 0.336 0.033 2 1 0.464 0.046
NEGATIVE VOLTAGE REGULATOR - VOLTAGE SENSE COMPARATOR
Ibias Tresp VTh VHys Input Bias Current Response Time Comparator Threshold Comparator Hysteresis 0.3V input 20mV overdrive 1.20 5 1.27 2 1 1.333 20
NEGATIVE VOLTAGE REGULATOR - DRIVER OUTPUT
Ilow Vhigh Vlow Low Output Current Output High Voltage Output Low Voltage VO < 3.5V I = 0.1mA; (VDig = 5V) I = -4mA 4 4.8 3.5 mA V V
LOOP BACK COMPARATOR
Vth Switching Threshold 0.45 0.50 0.55 V
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L6239
INTERNAL REGISTER DEFINITION Spin Control Register (Reg 0) The first (bits 0-8) is to program the current to the Reg: 0 Type: Write only.
BIT 0 1 2 3 4 5 6 7 8 LABEL SPIN DAC BIT 0 SPIN DAC BIT 1 SPIN DAC BIT 2 SPIN DAC BIT 3 SPIN DAC BIT 4 SPIN DAC BIT 5 SPIN DAC BIT 6 SPIN DAC BIT 7 SPIN RANGE Spindle current limit MSB Spindle transconductance loop gain range select, 0 = 4:1, 1= 20:1 Spindle current limit LSB
spindle motor to allow motor control and to present the "at speed" voltage for the charge pump. Often this will be used to limit the start-up current.
DESCRIPTION
@POR_ LOW 0 0 0 0 0 0 0 0 0
System Input Register (Reg 1) Reg: 1 Type: Write only.
BIT 0 1 2 3 4 5 6 7 8 9 10 11 LABEL SLEEP BRAKE PWM/LINEAR SINGLE/MULTI ENABLE CLK RESPHASE TRIST di CLKDIV2 ENABLE NEG TIME2X TEST PIN1 TEST PIN2 DESCRIPTION A0 puts the spindle into a high impedance state A1 turns on all lower spindle drivers to brake the spindle Selects either PWM (1) or Linear (0) modes of operation 1 selects phase. A for zero crossings, 0 selects all three phases Enables (1) the SPIN CLK pulses to increment the spindle counter Logic low to reset spindle counter Logic low to tristate BEMF DET output. Logic low - sys clk; logic high - half system clock Enables Negative Voltage circuitry (when set to 1). Logic low - masking time equal to 512 cycles of sys clk. Logic high masking time equal to 1024 cycles of sys clk. Test pin Test pin @POR_ LOW 0 0 0 0 0 0 0 0 0 0 0 0
System Input Register (Reg 2) Reg: 2 Type: Read only.
BIT 0 1 2 3 4 5 6 7 LABEL BEMF A BEMF B BEMF C IN X IN Y IN Z THERM_WARN LOOP_BACK DESCRIPTION Phase A zero crossing detected Phase B zero crossing detected Phase C zero crossing detected Grey code counter bit X Grey code counter bit Y Grey code counter bit Z Thermal shutdown warning. This occurs approximately 25C before the device goes into thermal shutdown. If PWM bit is set to 0, this bit represent the status of the loopback comparator @POR 0 0 0 0 0 0 0 0
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L6239
Register Select Table
INPUT: A3 - A0 0000 0001 0010 REGISTER SELECTED 0 1 2 TYPE WRITE WRITE READ
all registers to the "@POR" state (see register description). The L6239 assumes that a separate brake command must be issues to brake the spindle. Serial Interface The serial interface is designed to be compatible with the Intel 80196 (and other similar micros) serial interface but is capable of faster data rates, up to 10MHz. All read and write operations must consists of 16 bits, with the 80196 this would be two 8 bit accesses. The first four bits are address and the next 12 are data. If the address is a read register, then the L6239 will use the SCLK from the system to shift out 12 bits of data from the addressed register. The system must provide 16 SCLK pulses to insure that the read operation completes. The SDIO line is capable of driving a 60pf load.
Min. 100 100 100 100 10 10 30 30 10 10 30 30 100 100 40 100 50 0.1 60 30 30 50 50 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns % s
CIRCUIT OPERATION General This device includes a sensorless spin driver, power sequencing with dynamic braking and serial interface for a microprocessor. The device is register based to eliminate single point interconnects where ever possible. It is designed to operate with a 12V power supply. POR When POR goes low, the L6239 resets itself and
Symbol tRWS tSLS tRWH tSLH tSCKD tRWD tAS tDS tAH tDH tSDZ tRWZ tPER tREC (*) tDUT tSCLK Description R/W setup time to SCLK going high SLOAD setup time to SCLK going high R/W hold time after SCLK going high SLOAD hold time after SCLK going high SCLK high to Data Valid
R/W High to Data Valid Data bit D [0] valid from HiZ Address setup time to SCLK going high Data setup time to SCLK going high Address hold after SCLK going high Data hold time after SCLK going high SDIO tri-state after SLOAD going high SDIO tri-state afterR/W going low Minimum SCLK period Recycle - Time between successive accesses Clock duty cycle SCLK Clock timing
(*) For 10MHz system clock operation (in other words, 1 or more clock cycles of SCLK).
Serial Interface Truth Table
R/W 1 0 0 1 SLOAD 1 1 0 0 SDIO Tri-state (Port un-selected) Tri-state (Port un-selected) Address/Data input Data output DIRECTION Tri-state Tri-state Input Output
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L6239
Figure 1: Serial Write Timing Diagram
R/W
tRWS
tRWH
SLOAD
tSLS
tSLH
tPER SCLK
SDIO A0
4 bit address (FIXED) A1 A2 A3 D0 D1 D2 D3
12 bit address (FIXED) D4 D5 D6 D7 D8 D9 D10
D94IN121
D11
tAS
tAH
tDS tDH
Figure 2: Serial Read Timing Diagram
tSLS R/W tRWS
tRWH
tRWS
SLOAD
tPER SCLK
tRWD SDIO A0 INPUT A1 A2 A3 HiZ D0 D1
tSCKD OUTPUT D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
D94IN122
tAS
tAH
The write cycle has a fixed address and data length. Four bits of address and 12 bits of data must be clocked in to allow the data to be loaded into the desired register. The write cycle is initiated by setting SLOAD and R/W low. Setting R/W low causes the SDIO line to be tristated for data input. SLOAD low enables the internal counter to increment on the rising edge of SCLK. The address and data are clocked into the chip serially on each rising edge of SCLK as shown above. when both the 4 bits of address and the 12 bits of the data have been clocked in, then the address register will be written to with the provided data. Setting SLOAD high will clear theinternal logic and tri-state the SDIO line. This also provides a way of safely aborting a write by simply forcing SLOAD high.
NOTE: SLOAD must be kept low during the entire duration of the 16 write clocks.
The read cycle is initiated by setting SLOAD low and clocking in a valid read address. Only four bits of address are necessary, if more than four bits are clocked in, the four MSBs will be ignored (i.e. only the first four bits will be used). If a valid address is detected, the rising edge of R/W will liad the desired register into the internal serial/parallel register is then serially clocked out on every rising edge of SCLK (LSB is clocked out first). Additional padded bits clocked out will be zero.
NOTE: If SLOAD is set low with R?W high, the current contents of the internal shift register can be clocked out. This is useful for a "read back" of the data last written into the required register.
Figure 3, illustrates the case where the serial port is deselected while reading data. During a read mode, the mP is in tri-state and the L6239 is writing data on to the SDIO pin. If the
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L6239
Figure 3 Figure 4: System Level Interface
CLK
SCLK SDIO SLOAD R/W
R/W
DATA CS1
L6239
MICRO
SLOAD
R/W CS2
SCLK
SDIO
R/W CLK DATA
OTHER DEVICE
D95IN221
tSDZ
tRWD
tSCKD
tRWZ
D94IN123
CS
L6239 is deselected by bring SLOAD high, the serial port stops writing and assumes a tri-state condition after time tSTZ. When R/W goes low, the Serial Port stops writing to SDIO. This is actually a transparent operation, since SDIO is already tri-stated. Next, SLOAD goes low, selecting the L6239, but SDIO remains low since R/W is still low. When R/W goes high, the L6239 starts to write to SDIO with the data valid after time, tRWD. At the end of the read operation, R/W goes low and SDIO goes into tristate condition after time tRWZ. Power Devices/Spindl State Machine S_AU, S_B_U and S_C_U are the upper spindle drive transistors. They are active whenever the Figure 5
drive is in bipolar mode (Unipolar is not supported). S_A_L, S_B_L and S_C_L are the lower spindle drive transistors. They are active in bipolar drive. In linear mode the active transistor's gate drive is controlled so as to bring the current in the motor to the level set by the speed control compensation circuit or the current limit DAC. Activating the BRAKE mode turns on all the lower drivers. RESET places the state machine into a known state (see @POR column of register definitions). To increment the commutation state either Spin_Clock signal is clocked. Thermal Warning & Shutdown The Thermal (Shutdown) Warning is designed to allow the system to take any actions required
+5V ENABLE_NEG Vreg_Base Good decoupling must be used. e.g. minimum 22F
+ 20K 1.6K 43K 1.2V 5 10K + -
Vreg_Cur
2K 75 Load
100pF
2
22F
+5V
Vreg_Reg
20K
20K
L6239
D94IN124
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L6239
prior to the L6239 shut down at the Thermal Shutdown level. Once the Thermal SHutdown is triggered the spindle is tristated and the chip is reset (although the serial interface can still be used). No braking function taken place. The chip remains in this state with the serial interface available for access Once the device falls below the Thermal Warning temperature, the L6239 output stage is no longer tristated. If there is still sufficient motion in the motor, the P has the opportunuty to resynchronize the output Negative Voltage Regulator Support This device includes support for a negative voltage supply. The regulator uses a regulation technique, that generates an external negative voltage, but does not require an negative power supply. the diagram below shows the circuitry included in the L6239 to support the Regulator. The more lightly colored circuitry is the recommended external circuitry that actually creates the negative voltage. The circuit has been designed so that all external componentsa can be inexpensive. For example, the transistor needs only to be a 2N@()&A and the diode a 1N4148.
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L6239
PLCC44 PACKAGE MECHANICAL DATA
DIM. MIN. A B C D d1 d2 E e e3 e4 F F1 G M 1.16 0.46 0.71 0.101 0.046 14.99 1.27 12.7 1.98 0.018 0.028 0.004 17.4 16.51 3.65 4.2 2.59 0.68 16 0.590 0.050 0.500 0.078 mm TYP. MAX. 17.65 16.65 3.7 4.57 2.74 MIN. 0.685 0.650 0.144 0.165 0.102 0.027 0.630 inch TYP. MAX. 0.695 0.656 0.146 0.180 0.108
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L6239
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1995 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A.
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